Let me relax the design specs a little here. I don't want to be too strict.
Would this all be more feasible if we do 7 bits (128 levels) and reduce the frequency to 5mhz? That would mean the reference clock can go down to 640mhz. Does that help?
I'm also thinking that PWM may not be the right approach to this problem. I may need to reframe my question entirely.
Would this all be more feasible if we do 7 bits (128 levels) and reduce the frequency to 5mhz? That would mean the reference clock can go down to 640mhz. Does that help?
I'm also thinking that PWM may not be the right approach to this problem. I may need to reframe my question entirely.
Statistics: Posted by phennessey — Thu Apr 25, 2024 7:46 pm