That sounds like four interrupts for GPIO, not one. Though they only seem to document one for each core2.3.2. Interrupts
Each core is equipped with a standard ARM Nested Vectored Interrupt Controller (NVIC) which has 32 interrupt inputs.
Each NVIC has the same interrupts routed to it, with the exception of the GPIO interrupts: there is one GPIO interrupt per
bank, per core. These are completely independent, so e.g. core 0 can be interrupted by GPIO 0 in bank 0, and core 1 by
GPIO 1 in the same bank.
13 IO_IRQ_BANK0.
15 SIO_IRQ_PROC0
16 SIO_IRQ_PROC1
Not clear.
Statistics: Posted by pie_face — Tue Aug 06, 2024 12:17 pm