While the inter-core FIFO is the obvious thing to use - it was designed for the purpose - if you choose not to use it (perhaps already in use for something else), interrupting via one of the peripherals doesn't need any external wiring and is also easy enough.Now before I need to something clunky like write to one GPIO pin with one core , wire it up to its neighbour and use that pin as an input to trigger off, can someone point to some documentation of the feature I am sure unable to find but is sitting right in front of me?
Many of the peripherals have 'force' registers to force their IRQ active (for example, the GPIOI's PROC1_INTF0), and also most of them have interrupt sources that are permanently active if you never service them (for example, a PIO SM's Tx FIFO not full interrupt will always be active if you never write anything into the FIFO). So you can just pick some peripheral you aren't using, contrive for its interrupt to be always active (forced if necessary), then on one core you enable that interrupt (in the peripheral's interrupt enable register) and on the other core you clear the enable in your interrupt handler - using hw_set_bits()/hw_clr_bits() to do the enable/disable to avoid race hazards between the cores. Note here that every interrupt needs to be enabled in two places - in the peripheral itself (registers visible to both CPU cores) and in the NVIC (private to the core in question).
However, unless forced by circumstances to mess around with peripheral IRQs, the inter-core FIFO is easy to use. For simple cases, you can ignore the fact that it's a FIFO - just write arbitrary words into it on one core to trigger the interrupt in the other core, and then in the handling core pull a word out of it to acknowledge the interrupt.
Statistics: Posted by arg001 — Fri Aug 09, 2024 1:19 pm