If I run at a lower frequency, the error happens less, well, frequently.
I've added some more printfs:Summarizing those bits:
DMA_INTR: Interrupt Status (raw): Interrupt is set for channel 0 (TX)
TX DMA, channel number 0: dma_channel_config.ctrl (CTRL_TRIG):
* 24: channel is not BUSY
* 20:15: DREQ 16 as TREQ, which is DREQ_SPI0_TX
* 14:11: CHAIN_TO disabled
* 5: INCR_WRITE: each write is directed to the same, initial address.
* 4: INCR_READ: each read is directed to the same, initial address.
* 3:2: DATA_SIZE: SIZE_BYTE
* 1: HIGH_PRIORITY: no
* 0: DMA Channel Enabled
RX DMA, channel number 1: dma_channel_config.ctrl (CTRL_TRIG):
* 24: channel is BUSY
* 20:15: TREQ_SEL is DREQ 17: DREQ_SPI0_RX
* 14:11: CHAIN_TO disabled
* 5: INCR_WRITE: the write address increments with each transfer
* 4: INCR_READ: each read is directed to the same, initial address.
* 3:2: DATA_SIZE: SIZE_BYTE
* 1: HIGH_PRIORITY: no
* 0: DMA Channel Enabled
SPI0 SSPCR0:
* (new!) 15:8 Serial Clock Rate: 3
* 3:0: Data Size Select: 8-bit data
SPI0 SSPCR1:
2: Device configured as master
1: Synchronous serial port operation enabled
0: Loop back mode: Normal serial port operation enabled.
SPI0 SSPSR:
4: not busy
3: Receive FIFO is not full
2: Receive FIFO is empty
1: Transmit FIFO is not full
0: Transmit FIFO is empty
SSPDMACR:
1: DMA for the transmit FIFO is enabled
0: DMA for the receive FIFO is enabled
I've added some more printfs:
Code:
3450841:FS2:prvAlignmentReadWriteTests:768: prvAlignmentReadWriteTests(pcMountPath=/sd0/2)3455387:FS2:spi_transfer_wait_complete:227: Notification wait timed out3455393:FS2:chk_dma:115: DMA is busy3455397:FS2:chk_dma:120: TRANSFER_COUNT: 13455401:FS2:chk_dma:121: TRANS_COUNT reload value (DBG_TCR): 5123455407:FS2:chk_dma:122: DREQ counter: 03455411:FS2:chk_dmas:131: RX DMA error3455414:FS2:spi_transfer_wait_complete:231: DMA_INTR: 0b000000000000000000000000000000013455422:FS2:spi_transfer_wait_complete:232: TX DMA CTRL_TRIG: 0b000000000000100000000000000000013455431:FS2:spi_transfer_wait_complete:234: RX DMA CTRL_TRIG: 0b000000010000100010001000001000013455440:FS2:spi_transfer_wait_complete:236: SPI SSPCR0: 0b000000000000000000000011000001113455448:FS2:spi_transfer_wait_complete:237: SPI SSPCR1: 0b000000000000000000000000000000103455456:FS2:spi_transfer_wait_complete:238: SPI_SSPSR: 0b000000000000000000000000000000113455464:FS2:spi_transfer_wait_complete:239: SPI_SSPDMACR: 0b00000000000000000000000000000011DMA_INTR: Interrupt Status (raw): Interrupt is set for channel 0 (TX)
TX DMA, channel number 0: dma_channel_config.ctrl (CTRL_TRIG):
* 24: channel is not BUSY
* 20:15: DREQ 16 as TREQ, which is DREQ_SPI0_TX
* 14:11: CHAIN_TO disabled
* 5: INCR_WRITE: each write is directed to the same, initial address.
* 4: INCR_READ: each read is directed to the same, initial address.
* 3:2: DATA_SIZE: SIZE_BYTE
* 1: HIGH_PRIORITY: no
* 0: DMA Channel Enabled
RX DMA, channel number 1: dma_channel_config.ctrl (CTRL_TRIG):
* 24: channel is BUSY
* 20:15: TREQ_SEL is DREQ 17: DREQ_SPI0_RX
* 14:11: CHAIN_TO disabled
* 5: INCR_WRITE: the write address increments with each transfer
* 4: INCR_READ: each read is directed to the same, initial address.
* 3:2: DATA_SIZE: SIZE_BYTE
* 1: HIGH_PRIORITY: no
* 0: DMA Channel Enabled
SPI0 SSPCR0:
* (new!) 15:8 Serial Clock Rate: 3
* 3:0: Data Size Select: 8-bit data
SPI0 SSPCR1:
2: Device configured as master
1: Synchronous serial port operation enabled
0: Loop back mode: Normal serial port operation enabled.
SPI0 SSPSR:
4: not busy
3: Receive FIFO is not full
2: Receive FIFO is empty
1: Transmit FIFO is not full
0: Transmit FIFO is empty
SSPDMACR:
1: DMA for the transmit FIFO is enabled
0: DMA for the receive FIFO is enabled
Statistics: Posted by carlk3 — Tue Aug 27, 2024 6:24 pm