I was of the understanding that it was pull downs that are the problem, not pull ups. Happy to be corrected.So, I've been designing (waiting for the chips to become available) some board that plug together, each with an RP2354 on them. I've been using 10k external pull-ups for data/address lines as well as various bus-signals across the boards. At different times in the clock-cycle, boards can flip to read or write data. Can I summarize what's been said and see if I got it right ?Is that correct ?
- If I continue to use external 10k pull-ups, the RP2354's on boards reading the current signal could potentially latch up (at about 2.1v, but still logic-high)
- If I move to using external 4.7k pull-downs instead, that latch-up issue disappears. I don't have a problem pulling up or down, I just want a determinate state.
- I should clear GPIO.IE when switching to read-mode on any GPIO.
Statistics: Posted by jamesh — Fri Aug 30, 2024 6:48 pm