Ah, that's a good idea -- I did this with the other PIO and it remained in lock-step, which made me think along the lines of a bad system oscillator too.Or the main clk_sys PLL could be unstable. Could be interesting to program up a PWM channel with the same divisor to output the same frequency as BCLK on a different pin - do the two pins remain in lock-step or does the PIO one drift relative to it?
I've now done it with PWM, and also with a loop transferring the value of the PLL locked flag
Code:
pll_sys->cs & PLL_CS_LOCK_BITSThis plot is the time period of PIO (blue), time period of PWM (black), and a GPIO that is high if the clk_sys PLL is unlocked (red).
Looks like we've found the culprit - thanks all.
(Disconnecting sys clock from PLL or removing the divisor from PIO was not possible unfortunately, as the problem only occurs in the context of a bigger hardware system where I don't have the flexibility to slow things down.)
Statistics: Posted by cgj — Sat Aug 31, 2024 6:47 pm