I doubt anyone can do 40 nm silicon that will give very good ENOB for SAR ADCs without some form of calibration after it is baked. Getting to that stage will need an appropriate ADC IP block that has all the patent/IP licensing nicely sorted out, plus other stuff to support that.
I recall reading Microchip engineers in an old article marvelling about how their colleagues managed to produce high performance peripherals that they didn't thought was possible. Calibration and triming -- there are many tricks that IC designers know and non-IC designers like me don't. These days Microchip puts many calibration parameters along with the chip ID in their MCUs, acquired during packaging and test. I looked at a STM32H723VE datasheet, 1.1V core class with good ADC performance. I doubt they got to that with just silicon layout alone.
Browse this paper:
Low Power SAR ADC Design with Digital Background Calibration Algorithm
https://www.mdpi.com/2073-8994/12/11/1757
Designed on 40 nm, calibration improves ENOB from ~8 bits to ~11 bits -- sounds familiar. Also see Figure 4 Unit capacitor mismatch Monte Carlo simulation. The 3 sigma variation range just about matches the plus minus 6% that Espressif quoted in one of their brief ESP32 datasheets. Question is, can 40 nm processes do significantly bettter than that, does one exist?
Source the IP block and get the packaging and test resources to make it happen. Sure, it can be done, but at what added cost? Let's face it, we're not going to get the kind of ADC an STM32H723VE has. Folks like me just pick an MCU appropriate for the task. But at the same time I am also very interested to learn how others are using the ADC in ways that minimizes the impact of its limitations.
I recall reading Microchip engineers in an old article marvelling about how their colleagues managed to produce high performance peripherals that they didn't thought was possible. Calibration and triming -- there are many tricks that IC designers know and non-IC designers like me don't. These days Microchip puts many calibration parameters along with the chip ID in their MCUs, acquired during packaging and test. I looked at a STM32H723VE datasheet, 1.1V core class with good ADC performance. I doubt they got to that with just silicon layout alone.
Browse this paper:
Low Power SAR ADC Design with Digital Background Calibration Algorithm
https://www.mdpi.com/2073-8994/12/11/1757
Designed on 40 nm, calibration improves ENOB from ~8 bits to ~11 bits -- sounds familiar. Also see Figure 4 Unit capacitor mismatch Monte Carlo simulation. The 3 sigma variation range just about matches the plus minus 6% that Espressif quoted in one of their brief ESP32 datasheets. Question is, can 40 nm processes do significantly bettter than that, does one exist?
Source the IP block and get the packaging and test resources to make it happen. Sure, it can be done, but at what added cost? Let's face it, we're not going to get the kind of ADC an STM32H723VE has. Folks like me just pick an MCU appropriate for the task. But at the same time I am also very interested to learn how others are using the ADC in ways that minimizes the impact of its limitations.
Statistics: Posted by katak255 — Mon Sep 30, 2024 4:08 am