I suspect your problem with the IRQs racing is caused by your use of the PIO clock divider. I haven't tested it, but I would expect that with both of the SMs doing "wait 1 irq" and x1 clock dividers, they would both proceed when the IRQ is triggered. The clock divider is not a divider, it's an enable (ie. all SMs share the same clock but if using an x2 divider then that SM only executes on alternate clocks). So unless your SMs happen to be synchronized and both executing on the same clock cycles, one of them will run first, clear the IRQ, and then when the second one executes the IRQ is no longer active.
So if this analysis is correct, you should be able to fix it either by seting the clkdiv to 1 (and getting the ADC clock rate you need by adding delay to the PIO instructions), or else by synchronizing them with pio_clkdiv_restart_sm_mask().
I somewhat suspect that there might be an easier way to structure the whole problem (so you don't need two SMs in the first place), but I haven't studied it in detail to be able to make a suggestion.
So if this analysis is correct, you should be able to fix it either by seting the clkdiv to 1 (and getting the ADC clock rate you need by adding delay to the PIO instructions), or else by synchronizing them with pio_clkdiv_restart_sm_mask().
I somewhat suspect that there might be an easier way to structure the whole problem (so you don't need two SMs in the first place), but I haven't studied it in detail to be able to make a suggestion.
Statistics: Posted by arg001 — Tue Feb 25, 2025 8:52 am