What sources are you using, and in what context?Thanks, looking in to that right now.
Unfortunately all sources that I am finding say that the CS pin should be held low for the entire transaction.
I've just checked ARM, Intel, STM, Microchip, TI etc, they are all doing the same for continuous transmission:
Motorola SPI Format/Protocol mode 0 and 2: pulse CS between frames
Motorola SPI Format/Protocol mode 1 and 3: keep low CS between frames
An example from Intel (Motorola mode 0 and 3 only):
Statistics: Posted by gmx — Sat Apr 19, 2025 7:09 pm