ADC doesn't stop at a bad conversion, in FIFO mode it just marks bit 15 of the results for eventual bad conversions.The error bit on the ADC is not set, so I don't think it's stopping due to a bad conversion.
ADC: FIFO Register
Conversion result FIFO
31:16 Reserved
15 ERR: 1 if this particular sample experienced a conversion error. Remains in the
same location if the sample is shifted.
14:12 Reserved
11:0 VAL
Statistics: Posted by gmx — Sat Apr 26, 2025 7:25 pm