General • Re: Trouble with DMA timings <> PIO <> PSRAM latency

The reason the buffer is not on PSRAM is because I havn't pushed it (since it doesn't work). But here's how I declare it locally:

Code:

uint8_t __attribute__((section(".psram_bss"))) buffer[BUFF_SIZE];

And that buffer is directly passed to common_hal_imagecapture_parallelimagecapture_singleshot_capture? If so then it's probably the PIO FIFO's overrunning while the system is accessing code in flash (and thus blocking the QSPI).

It's probably a better idea to have 2 small-ish buffers in SRAM and write to them first. With DMA chaining this is fairly simple to do on the RP2350. Alternatively you might be able to starve the CPU by setting the BUS_PRIORITY register for the DMA to high, though I've never done that.

You should also take a look at the debug registers for bus stalls and FIFO overruns, BUSCTRL.PERFSEL1 and PIO.FDEBUG to debug this further.

Statistics: Posted by Tharre — Fri May 30, 2025 1:35 am

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