one thing that comes to mind, is the direction of the change
if we assume that internally, the divisor is implemented with just a counter and a == test
and lets say its set to /5 and the count is 4, and you change it to /1
then it will miss the ==5 test, and you just wont get another clock cycle until the counter rolls over
and its a 24bit integer component to the divisor, so that will cause up to 16,777,216 clock cycles of extra delay, any time you reduce the divisor
which comes out to about 134ms if the input is 125mhz
if we assume that internally, the divisor is implemented with just a counter and a == test
and lets say its set to /5 and the count is 4, and you change it to /1
then it will miss the ==5 test, and you just wont get another clock cycle until the counter rolls over
and its a 24bit integer component to the divisor, so that will cause up to 16,777,216 clock cycles of extra delay, any time you reduce the divisor
Code:
> Math.pow(2,24) / 1250000000.134217728Statistics: Posted by cleverca22 — Sun Jun 08, 2025 3:42 am