Interfacing (DSI, CSI, I2C, etc.) • Multiple MCP2517FD CAN Controller

Code:

/dts-v1/;/plugin/; / {compatible = "brcm,bcm2835";/* ---------- 1. pinctrl for the CS lines ---------- */fragment@0 {target = <&spi0_cs_pins>;/* Allow four entries instead of two */frag0: __overlay__ {brcm,pins = <8 7 25 24>;};};/* ---------- 2. update the SPI0 controller ---------- */fragment@1 {target = <&spi0>;frag1: __overlay__ {/* phandle, gpio#, flags (1 = GPIO_ACTIVE_LOW) */cs-gpios = <&gpio 8 1>,  /* CS0 */            <&gpio 7 1>,  /* CS1 */            <&gpio 25 1>, /* CS2 */            <&gpio 24 1>; /* CS3 */num-cs   = <4>;status   = "okay";};};/* ---------- 3. optional: “no_miso” helper ---------- */fragment@2 {target = <&spi0_pins>;/* placed in the dormant branch, activated by dtparam=no_miso */__dormant__ {/* Keep SCLK (GPIO 11) and MOSI (GPIO 10) only */brcm,pins = <10 11>;};};/* ---------- 4. dtparam overrides ---------- */__overrides__ {/* brcm,pins cells are 4 bytes each; cs-gpios groups are 12 bytes */cs0_pin = <&frag0>,"brcm,pins:0",           <&frag1>,"cs-gpios:4";cs1_pin = <&frag0>,"brcm,pins:4",           <&frag1>,"cs-gpios:16";cs2_pin = <&frag0>,"brcm,pins:8",           <&frag1>,"cs-gpios:28";cs3_pin = <&frag0>,"brcm,pins:12",           <&frag1>,"cs-gpios:40";no_miso = <0>,"=2";      /* hides MISO (GPIO 9) when set */};};

Code:

// SPDX-License-Identifier: (GPL-2.0 OR MIT)/dts-v1/;/plugin/;#include <dt-bindings/gpio/gpio.h>#include <dt-bindings/interrupt-controller/irq.h>#include <dt-bindings/pinctrl/bcm2835.h>/ {compatible = "brcm,bcm2835";/* SPI0 ‑ default CS0 / CS1 */fragment@0 {target = <&spidev0>;__dormant__ {status = "disabled";};};fragment@1 {target = <&spidev1>;__dormant__ {status = "disabled";};};/* SPI1 ‑ CS0 / CS1 / CS2 */fragment@2 {target-path = "spi1/spidev@0";__dormant__ {status = "disabled";};};fragment@3 {target-path = "spi1/spidev@1";__dormant__ {status = "disabled";};};fragment@4 {target-path = "spi1/spidev@2";__dormant__ {status = "disabled";};};/* SPI0 ‑ optional CS2 / CS3 (require spi0‑4cs overlay or CM5/Pi5 pins) */fragment@15 {target-path = "spi0/spidev@2";__dormant__ {status = "disabled";};};fragment@16 {target-path = "spi0/spidev@3";__dormant__ {status = "disabled";};};/* ----------------------------------------------------------------- *  Pin, clock and CAN controller template fragments (unchanged) * ----------------------------------------------------------------- */fragment@8 {target = <&gpio>;__overlay__ {mcp251xfd_pins: mcp251xfd_pins {brcm,pins = <25>;          /* overridden per‑instance */brcm,function = <BCM2835_FSEL_GPIO_IN>;};};};fragment@9 {target-path = "/clocks";__overlay__ {clk_mcp251xfd_osc: mcp251xfd-osc {#clock-cells = <0>;compatible = "fixed-clock";clock-frequency = <40000000>; /* overridden if needed */};};};/* Template CAN node – retargeted to spi0 / spi1 per override */mcp251xfd_frag: fragment@10 {target = <&spi0>;        /* default bus, overridden for spi1 */__overlay__ {status = "okay";#address-cells = <1>;#size-cells = <0>;mcp251xfd: mcp251xfd@0 {compatible = "microchip,mcp251xfd";reg = <0>;                      /* chip‑select, overridden */pinctrl-names = "default";pinctrl-0 = <&mcp251xfd_pins>;spi-max-frequency = <20000000>;  /* overridden via speed= */interrupt-parent = <&gpio>;interrupts = <25 IRQ_TYPE_LEVEL_LOW>; /* overridden */clocks = <&clk_mcp251xfd_osc>;};};};/* Optional RX‑INT fragment (kept for completeness) */fragment@11 {target = <&mcp251xfd>;mcp251xfd_rx_int_gpios: __dormant__ {microchip,rx-int-gpios = <&gpio 255 GPIO_ACTIVE_LOW>;};};/* Optional transceiver enable fragments (kept) */fragment@12 {target = <&gpio>;__dormant__ {mcp251xfd_xceiver_pins: mcp251xfd_xceiver_pins {brcm,pins = <255>;brcm,function = <BCM2835_FSEL_GPIO_OUT>;};};};fragment@13 {target-path = "/";__dormant__ {reg_mcp251xfd_xceiver: reg_mcp251xfd_xceiver {compatible = "regulator-fixed";regulator-name = "mcp251xfd_xceiver";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;gpio = <&gpio 4 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&mcp251xfd_xceiver_pins>;};};};fragment@14 {target = <&mcp251xfd>;__dormant__ {xceiver-supply = <&reg_mcp251xfd_xceiver>;};};/* ----------------------------------------------------------------- *  Parameter overrides – instances for each CS we support. * ----------------------------------------------------------------- */__overrides__ {/* SPI0 – CS0 */spi0-0 = <0>, "+0",<&mcp251xfd_frag>, "target:0=", <&spi0>,<&mcp251xfd>, "reg:0=0",<&mcp251xfd_pins>, "name=mcp251xfd_spi0_0_pins",<&clk_mcp251xfd_osc>, "name=mcp251xfd-spi0-0-osc",<&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi0_0_xceiver_pins",<&reg_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi0-0-xceiver",<&reg_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi0-0-xceiver";/* SPI0 – CS1 */spi0-1 = <0>, "+1",<&mcp251xfd_frag>, "target:0=", <&spi0>,<&mcp251xfd>, "reg:0=1",<&mcp251xfd_pins>, "name=mcp251xfd_spi0_1_pins",<&clk_mcp251xfd_osc>, "name=mcp251xfd-spi0-1-osc",<&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi0_1_xceiver_pins",<&reg_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi0-1-xceiver",<&reg_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi0-1-xceiver";/* SPI0 – CS2 (needs spi0‑4cs overlay) */spi0-2 = <0>, "+15",<&mcp251xfd_frag>, "target:0=", <&spi0>,<&mcp251xfd>, "reg:0=2",<&mcp251xfd_pins>, "name=mcp251xfd_spi0_2_pins",<&clk_mcp251xfd_osc>, "name=mcp251xfd-spi0-2-osc",<&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi0_2_xceiver_pins",<&reg_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi0-2-xceiver",<&reg_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi0-2-xceiver";/* SPI0 – CS3 (needs spi0‑4cs overlay) */spi0-3 = <0>, "+16",<&mcp251xfd_frag>, "target:0=", <&spi0>,<&mcp251xfd>, "reg:0=3",<&mcp251xfd_pins>, "name=mcp251xfd_spi0_3_pins",<&clk_mcp251xfd_osc>, "name=mcp251xfd-spi0-3-osc",<&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi0_3_xceiver_pins",<&reg_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi0-3-xceiver",<&reg_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi0-3-xceiver";/* SPI1 – CS0 */spi1-0 = <0>, "+2",<&mcp251xfd_frag>, "target:0=", <&spi1>,<&mcp251xfd>, "reg:0=0",<&mcp251xfd_pins>, "name=mcp251xfd_spi1_0_pins",<&clk_mcp251xfd_osc>, "name=mcp251xfd-spi1-0-osc",<&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi1_0_xceiver_pins",<&reg_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi1-0-xceiver",<&reg_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi1-0-xceiver";/* SPI1 – CS1 */spi1-1 = <0>, "+3",<&mcp251xfd_frag>, "target:0=", <&spi1>,<&mcp251xfd>, "reg:0=1",<&mcp251xfd_pins>, "name=mcp251xfd_spi1_1_pins",<&clk_mcp251xfd_osc>, "name=mcp251xfd-spi1-1-osc",<&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi1_1_xceiver_pins",<&reg_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi1-1-xceiver",<&reg_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi1-1-xceiver";/* SPI1 – CS2 */spi1-2 = <0>, "+4",<&mcp251xfd_frag>, "target:0=", <&spi1>,<&mcp251xfd>, "reg:0=2",<&mcp251xfd_pins>, "name=mcp251xfd_spi1_2_pins",<&clk_mcp251xfd_osc>, "name=mcp251xfd-spi1-2-osc",<&mcp251xfd_xceiver_pins>, "name=mcp251xfd_spi1_2_xceiver_pins",<&reg_mcp251xfd_xceiver>, "name=reg-mcp251xfd-spi1-2-xceiver",<&reg_mcp251xfd_xceiver>, "regulator-name=mcp251xfd-spi1-2-xceiver";/* ----------------------------------------------------------------- *  Shared parameter overrides (unchanged) * ----------------------------------------------------------------- */oscillator = <&clk_mcp251xfd_osc>, "clock-frequency:0";speed      = <&mcp251xfd>, "spi-max-frequency:0";interrupt  = <&mcp251xfd_pins>, "brcm,pins:0", <&mcp251xfd>, "interrupts:0";rx_interrupt = <0>, "+11", <&mcp251xfd_pins>, "brcm,pins:4", <&mcp251xfd_rx_int_gpios>, "microchip,rx-int-gpios:4";xceiver_enable = <0>, "+12+13+14", <&mcp251xfd_xceiver_pins>, "brcm,pins:0", <&reg_mcp251xfd_xceiver>, "gpio:4";xceiver_active_high = <&reg_mcp251xfd_xceiver>, "enable-active-high?";};};