We have a Compute Module 4 IO Board based product. An assembly house complains that layer thicknesses do not add up. The Compute Module 4 IO Board, and 5 KiCad files say that the PCB thickness is 1.56mm(below). But if I look the board Stack up I get 1.60mm or 1.57mm.
Yes, we are talking about 0.01-0.02millimeters. I wonder what tolerances are there in layers.
I have not modifier the Stack up.
"Board thickness : 1.56mm
Finished copper weight inners : 1oz
Finished copper weight outers : 1oz
Board finish : OSP
Material type : FR4
Colour of solder resists : Green
Colour of silk screens : White Only on the top side
Board to : UL94-V0
TG >=130
50R trace width 0.13mm@ 3GHz
90R diff pair width 0.147 spacing 0.253mm @ 2.5GHz
100R diff pair width 0.127 spacing 0.253mm @ 2GHz
"
The clipboard image is the Stack up.
Yes, we are talking about 0.01-0.02millimeters. I wonder what tolerances are there in layers.
I have not modifier the Stack up.
"Board thickness : 1.56mm
Finished copper weight inners : 1oz
Finished copper weight outers : 1oz
Board finish : OSP
Material type : FR4
Colour of solder resists : Green
Colour of silk screens : White Only on the top side
Board to : UL94-V0
TG >=130
50R trace width 0.13mm@ 3GHz
90R diff pair width 0.147 spacing 0.253mm @ 2.5GHz
100R diff pair width 0.127 spacing 0.253mm @ 2GHz
"
The clipboard image is the Stack up.
Statistics: Posted by Vadelma_Pi — Sun Aug 10, 2025 6:33 pm