For pacing trigger, there are 4 dedicated DMA timers.
How do they actually work? Initial X/Y values are 0/0: Does this mean stop?
Is the accumulator cleared when the register is written or is the phase arbitrary?
If not cleared, could something like 0/1 for X/Y drain the accumulator to 0, and it would start with a specific phase for next X > 0?
DMA: TIMER0, TIMER1, TIMER2, TIMER3 Registers
Pacing (X/Y) fractional timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every
sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.Code:
Bits Description Type Reset31:16 X: Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. RW 0x000015:0 Y: Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. RW 0x0000
Could they maybe be implemented somewhat like:
Code:
bool divide(uint16_t x, uint16_t y) { static uint16_t acc = 0; acc += x; if (acc >= y) { acc -= y; return true; } return false;}Code:
bool divide(bool enable, bool divider_restart, uint32_t divisor) { divisor &= ~0xff; // truncate to 16.8 static uint32_t counter = 0; const uint32_t one = 1 << 16; // 1.0 in 16.16 fixed-point if (divider_restart) { counter = 0; return false; } if (counter >= one) { counter -= one; return false; } else { counter -= one; counter += divisor; return enable; }}Statistics: Posted by PicoTinker — Sat Nov 01, 2025 6:43 am