There is an errata which is related to bus priorities, but looks not to be fixed in A4 (besides eventual workarounds in SDK):My faint suspect is that in A2 the bus prio was not implemented properly:
Reference RP2350-E27
Summary Bus priority controls apply to wrong managers for APB and FASTPERI arbiters.
Affects RP2350 A2, RP2350 A3, RP2350 A4
...
On the FASTPERI and APB arbiters, these signals are mis-wired, such that the wrong managers are
prioritised:
• BUS_PRIORITY.PROC0 controls DMA write priority
• BUS_PRIORITY.PROC1 controls core 0 load/store priority
• BUS_PRIORITY.DMA_R controls core 1 load/store priority
• BUS_PRIORITY.DMA_W controls DMA read priority
The BUS_PRIORITY controls are applied correctly for all other arbiters: ROM, SRAM, and XIP.
For example, if the DMA_R and DMA_W bits were set, this would prioritise DMA over processor access to ROM,
SRAM, and XIP. However, peripheral access would prioritise DMA read and core 1 load/store over DMA
write and core 0 load/store.
Statistics: Posted by gmx — Sun Dec 21, 2025 4:49 pm