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General • Re: RP2350 8 Slot Backplane with LVDS

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Sometimes AI is good for quick and simple things. It’s not perfect but it’s the general idea of what I was thinking. Based on your experience it seems like it will work okay.

What you said about the communication is exactly the way I was thinking. I just didn’t explain it clearly. One clock, one TX, and one RX on each Pico. Each clock transfers one bit and then gets shifted to the next Pico on the following clock cycle. Each slot counts the clock’s and knows which input and output data to take and to fill in. It removes the RS485 send and reply from each board. You end up with a constant delay that’s set by your packet size. That’s not my concept. It’s how EtherCAT works. I just think it’s possible to mimic that with the PIO. Now I just need to figure it all out.

Statistics: Posted by theoutfield — Thu Jan 08, 2026 7:34 pm



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