Interfacing (DSI, CSI, I2C, etc.) • High bandwidth interface for FPGA

The Secondary Memory Interface (SMI) has been very helpful in real-time data acquisition and motion control applications (Preempt_RT + SMI + FPGA). This deterministic high bandwidth communication interface to FPGA have been supported in all PIs until PI5. Therefore, our platform is stuck with CM4. PCIe is just too heavy for our application.

I was wondering is there any possibility for future PIs (RP1 successors) to have a high bandwidth parallel interface? Or we may need to move back to Xilinx Zynq platform.

Reference 1: What is SMI
viewtopic.php?t=280242

Reference 2: SMI real world application
https://github.com/cariboulabs/cariboulite

Statistics: Posted by wbzhong — Sun Jan 11, 2026 9:02 pm

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