RP1 will run the DSI interface at (BPP * pixelrate) / nlanes. This is the DDR bit-rate.is there a calculation sheet which would allow seeing the correlations? TI i.e. has them for some of there DSI products (either an excel sheet and/or some GUI based SW).
Knowing which parameter to change would be simpler than running a try&error type of test.
The table here encodes the times to enter and leave HS. The first column is lane bitrate in Mbps. The last 2 columns are LP->HS and HS->LP times for data lanes (assuming continuous clock), measured in byteclocks, where byteclock rate is bitrate/8 or (BPP * pixelrate) / (8 * nlanes).
We got those numbers from the PHY datasheet; it's presumably what the PHY actually does when programmed up with the associated "hsfreqrange" code. Not sure why they're not all monotonic -- maybe some rounding error.
Adding the last two numbers plus ceil(6/nlanes) (for a HS packet header and footer) then converting from byteclocks to pixels should (I think, unless I've missed something) give the threshold for when the DSI Host would drop to LP11. The actual decision is automated.
Statistics: Posted by njh — Thu Aug 01, 2024 12:33 pm