Other RP2040 boards • Re: Custom RP2350 Board

Thank you both very much!

a) I think your ground cutout under the 1V1 switcher is larger than necessary. I presume you've done it in the first place to minimise capacitive coupling to the VREG_LX trace (which seems reasonable). However, there's no point excluding the ground under Pin1 of L2 and the positive ends of C19/C20, as those are all deliberately applying capacitance to ground! So personally, I'd make it much narrower.

When adding the cutouts to the inner layers I was referring to Figure 26 of the RP2350 datasheet. I understand your point and it makes sense. Maybe the datasheet is to strict/conservative about that point. I will think about it for a bit.

b) I don't like push-buttons that rely on the on-chip pull-up of the GPIO input: risk of pick-up from outside influences (and hence failing an EMC immunity test). I'd have an explicit pull-up resistor.

Not much of discussion here I guess, thank for the hint.

Finally, I note that you are supplying the 1V1 regulator from +3V3, rather than VSYS (as allowed by the datasheet, and presumably offering greater efficiency). Was that a deliberate decision to be conservative?

My VSYS can vary from 5V (via USB) to up to 32V (max allowed voltage for the buck-converter. Typical input voltage is expected to be 12V. In general, I tried to design the circuit a bit robust, so that not a wrongly plugged in power adapter causes any harm.
From the datasheet, I see the max input voltage for the Core Voltage regulator is 5.5V (Figure 20). As my input my be higher, I used the 3.3V from the buck-converter.

Personally I use a ring of many more stitchthrus under the RP2xxx device to get rid of heat. But not the one in the middle as I've seen that cause problems in reflow in the past.

Duly noted and changed. Thank you.

Statistics: Posted by Chros — Fri Jun 20, 2025 8:02 am

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