DSI is not a trivial interface. Consider it more like ethernet where you can have multiple data streams present in parallel, so your logic analyser is of limited use. You've also got multiple options within the protocol definitions.
As documented in https://pip.raspberrypi.com/categories/ ... isplay.pdf, CM4 will be slightly altering the panel timings due to the DSI block being fed by an integer divider off a 3GHz clock.
If you are using the stock timings and my calculations are right, then the HFP of 160 will have been increased to 274, and a pixel clock of 55555kHz. If so then you'll be hit by the issue in https://github.com/raspberrypi/linux/issues/6922 that I'm still investigating. The quickest way to confirm would be to run "kmstest --flip" and check the frame rate reported. If it's higher than the expected 60fps, then that would imply so, and it'd be useful to dump out /sys/kernel/debug/dri/1/dsi1_regs so I can confirm.
As documented in https://pip.raspberrypi.com/categories/ ... isplay.pdf, CM4 will be slightly altering the panel timings due to the DSI block being fed by an integer divider off a 3GHz clock.
If you are using the stock timings and my calculations are right, then the HFP of 160 will have been increased to 274, and a pixel clock of 55555kHz. If so then you'll be hit by the issue in https://github.com/raspberrypi/linux/issues/6922 that I'm still investigating. The quickest way to confirm would be to run "kmstest --flip" and check the frame rate reported. If it's higher than the expected 60fps, then that would imply so, and it'd be useful to dump out /sys/kernel/debug/dri/1/dsi1_regs so I can confirm.
Statistics: Posted by 6by9 — Thu Aug 07, 2025 5:05 pm