General • Re: out of sync issue

Can it happen that on one of the cores I write a value into a variable and the other core doesn't see that? Not until I repeat the whole process? And no ISB/DSB/DMB helps about it.

Might be from compiler if variables are not declared volatile.

Mea culpa, mea maxima culpa

(Volatile here doesn't make any difference, I saw in the .dis files that all variables are written to SRAM immediately. )

I forgot to mention that the core, that handles IRQs also initiates DMAs (64x 32bit transfers in each 100us for ~15ms and then ~5ms pause). Anyway, for some reason the BUSPRIORITY was set to the other core, so this core was competing with the DMA and the other core simply överruled them.

Now, that I set the BUSPRIORITY to this core, it works as expected.

Statistics: Posted by dikdom — Thu Jan 15, 2026 9:03 pm

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